Invention Grant
- Patent Title: Thread associated memory allocation and memory architecture aware allocation
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Application No.: US15743635Application Date: 2016-07-05
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Publication No.: US10725824B2Publication Date: 2020-07-28
- Inventor: Keith Lowery
- Applicant: RAMBUS, INC.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lowenstein Sandler LLP
- International Application: PCT/US2016/040970 WO 20160705
- International Announcement: WO2017/011223 WO 20170119
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06F8/41 ; G06F9/30 ; G06F9/38 ; G06F12/02

Abstract:
A method and system for thread aware, class aware, and topology aware memory allocations. Embodiments include a compiler configured to generate compiled code (e.g., for a runtime) that when executed allocates memory on a per class per thread basis that is system topology (e.g., for non-uniform memory architecture (NUMA)) aware. Embodiments can further include an executable configured to allocate a respective memory pool during runtime for each instance of a class for each thread. The memory pools are local to a respective processor, core, etc., where each thread executes.
Public/Granted literature
- US20180203734A1 THREAD ASSOCIATED MEMORY ALLOCATION AND MEMORY ARCHITECTURE AWARE ALLOCATION Public/Granted day:2018-07-19
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