Invention Grant
- Patent Title: Process integration approach of selective tungsten via fill
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Application No.: US16252100Application Date: 2019-01-18
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Publication No.: US10727119B2Publication Date: 2020-07-28
- Inventor: He Ren , Feiyue Ma , Yu Lei , Kai Wu , Mehul B. Naik , Zhiyuan Wu , Vikash Banthia , Hua Ai
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/285 ; H01L23/532 ; H01L23/522
Abstract:
Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.
Public/Granted literature
- US20190157145A1 PROCESS INTEGRATION APPROACH OF SELECTIVE TUNGSTEN VIA FILL Public/Granted day:2019-05-23
Information query
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