Invention Grant
- Patent Title: Method for manufacturing substrate terminal board for mounting semiconductor element
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Application No.: US16349450Application Date: 2017-11-13
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Publication No.: US10734562B2Publication Date: 2020-08-04
- Inventor: Masaya Nakagawa , Shojiro Wakabayashi , Mamoru Yuasa , Toshifumi Watanabe
- Applicant: SUNCALL CORPORATION , STANLEY ELECTRIC CO., LTD.
- Applicant Address: JP Kyoto JP Tokyo
- Assignee: SUNCALL CORPORATION,STANLEY ELECTRIC CO., LTD.
- Current Assignee: SUNCALL CORPORATION,STANLEY ELECTRIC CO., LTD.
- Current Assignee Address: JP Kyoto JP Tokyo
- Agency: Kenealy Vaidya LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@980af9e
- International Application: PCT/JP2017/040692 WO 20171113
- International Announcement: WO2018/092704 WO 20180524
- Main IPC: H01L33/64
- IPC: H01L33/64 ; H01L33/62

Abstract:
Some embodiments provide a substrate terminal board in which the number of components is reduced by utilizing a conductor board per se constituting the substrate terminal board while ensuring heat dissipation, and which has a simple structure. Heat-dissipation fins can be cut and raised at a plurality of positions around element mounting portions of an upper-substrate conductor board, thus providing heat-dissipation fins and heat-dissipation openings. The upper-substrate conductor board can be coated with a paint film to form an upper substrate. A lower-substrate conductor board can be coated with the paint film to form a lower substrate. In a pressing/heating process, the lower substrate and the upper substrate can overlap each other and be vertically pressed while the lower substrate and the upper substrate are heated to completely cure the paint film, thereby causing the paint film on the lower substrate and the paint film on the upper substrate to adhere to each other.
Public/Granted literature
- US20190341538A1 METHOD FOR MANUFACTURING SUBSTRATE TERMINAL BOARD FOR MOUNTING SEMICONDUCTOR ELEMENT Public/Granted day:2019-11-07
Information query
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