Power module includes: first transistors Q1, Q4 forming at least one half bridge, and disposed at upper and lower arms thereof; second transistors QM1, QM4 of which drains are respectively connected to gates G1 and G4 sides of the first transistors, and sources are respectively connected to the sources S1, S4 sides thereof; source signal wiring patterns SSP1, SSP4 respectively connected to the sources S1, S4 of the first transistors; first connected conductors MSW1, MSW4 for respectively connecting between the source signal wiring patterns and the sources of the second transistors; second gate signal wiring patterns MGP1, MGP4 respectively connected to gates MG1, MG4 of the second transistors; and second connected conductors MGW1, MGW4 for respectively connecting between the gate signal wiring patterns and the gates of the second transistors. Lengths of the first connection conductors are respectively equal to or shorter than lengths of the second connection conductors.