The present disclosure provides a control circuit, where the control circuit includes: a signal detection unit, a zero-crossing detection (ZCD) signal acquisition unit, a pulse width modulation (PWM) control signal generation unit, and a signal processing unit; where the signal detection unit, the ZCD signal acquisition unit, the PWM control signal generation unit and the signal processing unit are connected in cascade. The control circuit provided in the present disclosure reduces processing delay of a ZCD signal and improve signal a processing accuracy of a power factor correction (PFC) system.