Resistive random access memory device and method for performing memory operations
Abstract:
A resistive random access memory device which includes a resistive random access memory array, a sense amplifier and a boosting circuit. The sense amplifier is coupled to the resistive random access memory array and is configured to sense a resistance value of the memory cell. The boosting circuit is coupled to the memory cell of the resistive random access memory array and is configured to boost a reset voltage in a boosting period of a reset period according to the resistance value of the memory cell. The boosting period is from beginning of the reset period, and the memory cell is biased with the reset voltage in the reset period to perform the reset operation. A method for a reset operation on a resistive random access memory device is also introduced.
Information query
Patent Agency Ranking
0/0