Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.