公开(公告)号：US09735089B2

公开(公告)日：2017-08-15

申请号：US14864433

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Hemanth K. Dhavaleswarapu

IPC: H01L23/34 ,  H01L23/473 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/473 ,  H01L21/4882 ,  H01L23/145 ,  H01L23/5384 ,  H01L23/5387 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2225/06548 ,  H01L2225/06589

Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09659908B1

公开(公告)日：2017-05-23

申请号：US14937022

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shubhada H. Sahasrabudhe ,  Sandeep B Sane ,  Siddarth Kumar ,  Shalabh Tandon

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

公开(公告)号：US20210280495A1

公开(公告)日：2021-09-09

申请号：US16328614

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Shalabh Tandon

IPC: H01L23/40 ,  H01L23/427 ,  H01L21/48

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.

公开(公告)号：US20170133350A1

公开(公告)日：2017-05-11

申请号：US14937022

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Siddarth Kumar ,  Shalabh Tandon

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

公开(公告)号：US09953934B2

公开(公告)日：2018-04-24

申请号：US14971744

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Sandeep B Sane ,  Shubhada H. Sahasrabudhe ,  Shalabh Tandon

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.

公开(公告)号：US09930793B2

公开(公告)日：2018-03-27

申请号：US14227779

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Chuan Hu ,  Siddarth Kumar

IPC: H05K5/00 ,  H01L21/56 ,  H05K1/18 ,  H05K1/03 ,  H05K5/06 ,  H05K1/11 ,  H05K3/30 ,  H01L23/31

CPC classification number: H05K5/0095 ,  H01L21/56 ,  H01L23/3135 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0326 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/303 ,  H05K5/065 ,  H05K2201/0195 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: Generally discussed herein are systems and apparatuses that can include a flexible substrate with a hermetic seal formed thereon. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a hermetic seal on a flexible substrate can include (1) forming an interconnect on a flexible substrate, (2) situating a device on the substrate near the interconnect, or (3) selectively depositing a first hermetic material on the device or interconnect so as to hermetically seal the device within the combination of the interconnect and first hermetic material.

公开(公告)号：US20170092564A1

公开(公告)日：2017-03-30

申请号：US14864433

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Hemanth K. Dhavaleswarapu

IPC: H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/473 ,  H01L21/4882 ,  H01L23/145 ,  H01L23/5384 ,  H01L23/5387 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2225/06548 ,  H01L2225/06589

Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US11276625B2

公开(公告)日：2022-03-15

申请号：US16328614

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Shalabh Tandon

IPC: H01L23/367 ,  H01L23/40 ,  H01L21/48 ,  H01L23/427

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.

公开(公告)号：US10748844B2

公开(公告)日：2020-08-18

申请号：US15859331

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Shawna M. Liff

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  G02B6/122 ,  G02B6/12 ,  G02B6/42

Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.

公开(公告)号：US20150282341A1

公开(公告)日：2015-10-01

申请号：US14227779

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Chuan Hu ,  Siddarth Kumar

IPC: H05K5/00 ,  H05K1/11 ,  H05K5/06 ,  H05K1/18 ,  H05K3/30 ,  H05K1/03

CPC classification number: H05K5/0095 ,  H01L21/56 ,  H01L23/3135 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0326 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/303 ,  H05K5/065 ,  H05K2201/0195 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: Generally discussed herein are systems and apparatuses that can include a flexible substrate with a hermetic seal formed thereon. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a hermetic seal on a flexible substrate can include (1) forming an interconnect on a flexible substrate, (2) situating a device on the substrate near the interconnect, or (3) selectively depositing a first hermetic material on the device or interconnect so as to hermetically seal the device within the combination of the interconnect and first hermetic material.

Abstract translation: 这里通常讨论的是可以包括其上形成有气密密封的柔性基底的系统和装置。 本公开还包括制造和使用系统和装置的技术。 根据一个实例，在柔性基板上进行气密密封的技术可以包括（1）在柔性基板上形成互连，（2）将布置在基板上的装置定位在互连件附近，或（3）选择性地沉积第一密封 材料在装置或互连上，以便在互连和第一密封材料的组合内气密地密封装置。