Invention Grant
- Patent Title: Electronic apparatus and layout method for integrated circuit
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Application No.: US16655177Application Date: 2019-10-16
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Publication No.: US10755022B2Publication Date: 2020-08-25
- Inventor: Chien-Chin Huang , Shih-Min Tseng
- Applicant: Winbond Electronics Corp.
- Applicant Address: TW Taichung
- Assignee: Winbond Electronics Corp.
- Current Assignee: Winbond Electronics Corp.
- Current Assignee Address: TW Taichung
- Agency: JCIPRNET
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@6adef56e
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/398 ; G06F111/20

Abstract:
An electronic apparatus and a layout method for an integrated circuit (IC) are provided. The layout method for the IC includes: receiving layout information, analyzing the layout information to obtain a plurality of blank areas in the IC; presetting a plurality of dummy blocks which respectively have a plurality of sizes; selecting at least one of the dummy blocks to fill in each of the blank areas based on a center position of each of the blank areas according to a size of each of the blank areas and generating updated layout information; performing a layout density checking operation on the updated layout information to generate a checking result; and shrinking sizes of a plurality of setting dummy blocks in the IC according to the checking result and generating output layout information.
Public/Granted literature
- US20200125692A1 ELECTRONIC APPARATUS AND LAYOUT METHOD FOR INTEGRATED CIRCUIT Public/Granted day:2020-04-23
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