Invention Grant
- Patent Title: V-shape recess profile for embedded source/drain epitaxy
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Application No.: US16654906Application Date: 2019-10-16
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Publication No.: US10763366B2Publication Date: 2020-09-01
- Inventor: Chii-Horng Li , Chih-Shan Chen , Roger Tai , Yih-Ann Lin , Yen-Ru Lee , Tzu-Ching Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/78 ; H01L21/3065 ; H01L29/06 ; H01L29/08 ; H01L29/66

Abstract:
A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.
Public/Granted literature
- US20200052121A1 V-Shape Recess Profile for Embedded Source/Drain Epitaxy Public/Granted day:2020-02-13
Information query
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