公开(公告)号：US20230142157A1

公开(公告)日：2023-05-11

申请号：US18149267

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/41791 ,  H01L29/0847 ,  H01L21/30625 ,  H01L27/092 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/66545 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845

Abstract: A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

公开(公告)号：US11545562B2

公开(公告)日：2023-01-03

申请号：US16715347

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/70 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US11522050B2

公开(公告)日：2022-12-06

申请号：US17104938

申请日：2020-11-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui Fu Hsieh ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Jen Chen ,  Tzu-Chan Weng

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US11984478B2

公开(公告)日：2024-05-14

申请号：US17341745

申请日：2021-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu Wen Wang ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Jui Fu Hsieh ,  Dave Lo

IPC: H01L21/8238 ,  H01L25/065 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H10B10/00 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L25/0655 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H10B10/12 ,  H01L29/41791

Abstract: A method includes forming a first portion of a spacer layer over a first fin and a second portion of the spacer layer over a second fin, performing a first etching process to recess the first portion of the spacer layer with respect to the second portion of the spacer layer to form first spacers on sidewalls of the first fin, subsequently performing a second etching process to recess the second portion of the spacer layer with respect to the first spacers to form second spacers on sidewalls of the second fin, where the second spacers are formed to a height greater than that of the first spacers, and forming a first epitaxial source/drain feature and a second epitaxial source/drain feature between the first spacers and the second spacers, respectively, where the first epitaxial source/drain feature is larger than that of the second epitaxial source/drain feature.

公开(公告)号：US20210184019A1

公开(公告)日：2021-06-17

申请号：US17188698

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chih-Shan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L21/3065 ,  H01L27/088

Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

公开(公告)号：US20180337283A1

公开(公告)日：2018-11-22

申请号：US16048822

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD

Inventor： Chii-Horng Li ,  Chih-Shan Chen ,  Roger Tai ,  Yih-Ann Lin ,  Yen-Ru Lee ,  Tzu-Ching Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

公开(公告)号：US10038095B2

公开(公告)日：2018-07-31

申请号：US15235899

申请日：2016-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chii-Horng Li ,  Chih-Shan Chen ,  Roger Tai ,  Yih-Ann Lin ,  Yen-Ru Lee ,  Tzu-Ching Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

公开(公告)号：US12237403B2

公开(公告)日：2025-02-25

申请号：US18298055

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chih-Shan Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

公开(公告)号：US20210280581A1

公开(公告)日：2021-09-09

申请号：US17313590

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Wen Cheng ,  Chih-Shan Chen ,  Mu-Tsang Lin

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

公开(公告)号：US10651309B2

公开(公告)日：2020-05-12

申请号：US16048822

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chii-Horng Li ,  Chih-Shan Chen ,  Roger Tai ,  Yih-Ann Lin ,  Yen-Ru Lee ,  Tzu-Ching Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.