Invention Grant
- Patent Title: Vertical group III-N devices and their methods of fabrication
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Application No.: US16321722Application Date: 2016-09-30
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Publication No.: US10770575B2Publication Date: 2020-09-08
- Inventor: Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Pavel M. Agababov
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/055059 WO 20160930
- International Announcement: WO2018/063409 WO 20180405
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L29/778 ; H01L29/06 ; H01L29/08 ; H01L29/20 ; H01L29/423 ; H01L29/66

Abstract:
Vertical Group III-N devices and their methods of fabrication are described. In an example, a semiconductor structure includes a doped buffer layer above a substrate, and a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface. A drain region is disposed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region. A polarization charge inducing layer is disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the first portion of the polarization charge inducing layer.
Public/Granted literature
- US20200066893A1 VERTICAL GROUP III-N DEVICES AND THEIR METHODS OF FABRICATION Public/Granted day:2020-02-27
Information query
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