Invention Grant
- Patent Title: Beaded fin transistor
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Application No.: US16081572Application Date: 2016-04-01
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Publication No.: US10770593B2Publication Date: 2020-09-08
- Inventor: Gilbert Dewey , Tahir Ghani , Willy Rachmady , Jack T. Kavalieros , Matthew V. Metz , Anand S. Murthy , Chandra S. Mohapatra
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- International Application: PCT/US2016/025605 WO 20160401
- International Announcement: WO2017/171845 WO 20171005
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/8238 ; H01L29/08 ; H01L29/10 ; H01L29/423

Abstract:
Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.
Public/Granted literature
- US20190097055A1 BEADED FIN TRANSISTOR Public/Granted day:2019-03-28
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