Invention Grant
- Patent Title: Layered spacer formation for ultrashort channel lengths and staggered field plates
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Application No.: US16321411Application Date: 2016-09-30
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Publication No.: US10777671B2Publication Date: 2020-09-15
- Inventor: Han Wui Then , Sansaptak Dasgupta , Marko Radosavljevic
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/055020 WO 20160930
- International Announcement: WO2018/063399 WO 20180405
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/778 ; H01L29/08 ; H01L29/20 ; H01L29/40

Abstract:
Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.
Public/Granted literature
- US20200066889A1 LAYERED SPACER FORMATION FOR ULTRASHORT CHANNEL LENGTHS AND STAGGERED FIELD PLATES Public/Granted day:2020-02-27
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