Invention Grant
- Patent Title: Test probing structure
-
Application No.: US15789338Application Date: 2017-10-20
-
Publication No.: US10782318B2Publication Date: 2020-09-22
- Inventor: Mill-Jer Wang , Ching-Fang Chen , Sandeep Kumar Goel , Chung-Sheng Yuan , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee , Hung-Chih Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G01R1/073
- IPC: G01R1/073

Abstract:
A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
Public/Granted literature
- US20180038894A1 TEST PROBING STRUCTURE Public/Granted day:2018-02-08
Information query