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公开(公告)号：US11249112B2
公开(公告)日：2022-02-15
申请号：US16933576
申请日：2020-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Wei-Hsun Lin , Sen-Kuei Hsu , De-Jian Liu
Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
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公开(公告)号：US09453877B2
公开(公告)日：2016-09-27
申请号：US15098037
申请日：2016-04-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mill-Jer Wang , Kuo-Chuan Liu , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC classification number: G01R31/2893 , G01R1/0483 , G01R1/06722 , G01R31/2867 , G01R31/2875 , G01R31/318513
Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
Abstract translation: 提供了用于芯片单元的测试保持器，用于多个芯片单元的多站点保持框架和用于测试其芯片的方法。 所提出的用于同时测试多个芯片单元的多站点保持框架包括具有多个测试保持器的第一保持架。 多个测试夹具中的每一个包括一个包含多个芯片单元中的特定一个的保持器本体，以及形成在保持器主体上以当多个芯片单元中的特定一个插入保持器中时释放插入压力的压力释放装置 身体。
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公开(公告)号：US20150241508A1
公开(公告)日：2015-08-27
申请号：US14186107
申请日：2014-02-21
Applicant: Taiwan Semiconductor Manufacturing CO.,LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC classification number: H01L22/14 , G01R31/2889
Abstract: A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.
Abstract translation: 公开了包括信号强制路径，放电路径，接触探针，监测探针和开关模块的电路。 信号强制路径连接到信号源。 放电路径连接到放电电压端子。 接触探针接触未测试装置的垫模块。 监测探头产生与焊盘模块相关的监控电压。 开关模块在放电模式下工作，当监控电压未达到阈值电压时，将接触探头连接到放电路径，使得被测设备被放电并且在操作模式下操作以将接触探针连接到 当监视的电压达到阈值电压时，信号强制路径使得由信号源产生的信号被强制到被测设备。
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公开(公告)号：US20150241507A1
公开(公告)日：2015-08-27
申请号：US14189112
申请日：2014-02-25
Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Sen-Kuei Hsu , Chuan-Ching Wang , Hao Chen
IPC: G01R31/265 , G01R1/073 , G01R31/26
CPC classification number: G01R31/265 , G01R31/3025
Abstract: A method is disclosed that includes the operations outlined below. For a plurality of dies on a test fixture, an antenna distance between each of first antennas of one of the dies and every one of first antennas of the other dies is determined. The dies are categorized into die groups, wherein the antenna distance between each of the first antennas of one of the dies in one of the die groups and every one of the first antennas of the other dies in the same one of the die groups is larger than an interference threshold. Test processes are sequentially performed on the die groups. Each of the test processes is performed according to signal transmissions between the first antennas and second antennas of the under-test device each positionally corresponds to one of the first antennas.
Abstract translation: 公开了一种包括以下概述的操作的方法。 对于测试夹具上的多个管芯，确定一个管芯的每个第一天线与另一个管芯的每个第一天线之间的天线距离。 模具被分类为管芯组，其中一个管芯组中的一个管芯中的一个管芯的每个第一个天线之间的天线距离和另一个管芯组中的另一个管芯的每个第一个天线之间的天线距离较大 比干扰阈值。 在模具组上依次执行测试过程。 每个测试过程根据第一天线与被测设备的第二天线之间的信号传输进行，每个位置上对应于第一天线之一。
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公开(公告)号：US11340291B2
公开(公告)日：2022-05-24
申请号：US16912017
申请日：2020-06-25
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mill-Jer Wang , Kuo-Chuan Liu , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC: G01R31/28 , G01R31/3185 , G01R1/04 , G01R1/067
Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
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Patent Agency Ranking
公开(公告)号：US11199578B2
公开(公告)日：2021-12-14
申请号：US16858745
申请日：2020-04-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tang-Jung Chiu , Hung-Chih Lin , Mill-Jer Wang
Abstract: A testing apparatus for testing an integrated circuit package having a plurality of electrical terminals includes a base, a socket, a plurality of conductive pins and a plurality of conductive pillars. The base includes a plurality of electrical contacts. The socket is disposed on the base and includes a bended portion bended away from the base and a plurality of through holes distributed in the socket. The conductive pins are disposed in the through holes respectively and electrically connected to the electrical contacts, wherein each of the conductive pins protrudes from an upper surface of the socket for forming temporary electrical connections with one of the electrical terminals. The conductive pillars are disposed on the base and connected to the bended portion, wherein each of the conductive pillars electrically connects one of the conductive pins and one of the electrical contacts.
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公开(公告)号：US10718790B2
公开(公告)日：2020-07-21
申请号：US16378288
申请日：2019-04-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Wei-Hsun Lin , Sen-Kuei Hsu , De-Jian Liu
Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
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公开(公告)号：US10652987B2
公开(公告)日：2020-05-12
申请号：US15882256
申请日：2018-01-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Cheng
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
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9.发明申请公开(公告)号：US20180153026A1
公开(公告)日：2018-05-31
申请号：US15882256
申请日：2018-01-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Cheng
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
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公开(公告)号：US20180038894A1
公开(公告)日：2018-02-08
申请号：US15789338
申请日：2017-10-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Fang Chen , Sandeep Kumar Goel , Chung-Sheng Yuan , Chao-Yang Yeh , Chin-Chou Liu , Yun-Han Lee , Hung-Chih Lin
IPC: G01R1/073
CPC classification number: G01R1/07342 , G01R1/07378 , H01L2224/16225
Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
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