Invention Grant
- Patent Title: Semiconductor package with supported stacked die
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Application No.: US16072222Application Date: 2016-04-02
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Publication No.: US10796975B2Publication Date: 2020-10-06
- Inventor: Guo Mao
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Eversheds Sutherland (US) LLP
- International Application: PCT/CN2016/078407 WO 20160402
- International Announcement: WO2017/166325 WO 20171005
- Main IPC: H01L23/18
- IPC: H01L23/18 ; H01L23/31 ; H01L25/065 ; H01L23/00 ; H01L23/16

Abstract:
Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.
Public/Granted literature
- US20190035705A1 SEMICONDUCTOR PACKAGE WITH SUPPORTED STACKED DIE Public/Granted day:2019-01-31
Information query
IPC分类: