- Patent Title: Multilayer printed circuit board via hole registration and accuracy
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Application No.: US16601068Application Date: 2019-10-14
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Publication No.: US10811210B2Publication Date: 2020-10-20
- Inventor: Shinichi Iketani , Douglas Ward Thomas
- Applicant: SANMINA CORPORATION
- Applicant Address: US CA San Jose
- Assignee: Sanmina Corporation
- Current Assignee: Sanmina Corporation
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Julio M. Loza
- Main IPC: G06K9/62
- IPC: G06K9/62 ; G11C15/00 ; G11C17/10 ; G11C15/04 ; H01H85/12 ; H01H85/00 ; H01H85/143 ; H05K3/46 ; H01H85/055 ; H01H85/20 ; H01H85/30 ; H01H85/56 ; H05K1/11 ; H05K1/14 ; H05K3/00 ; H05K3/10 ; H05K3/40 ; H01H85/06 ; H01H1/58 ; H01H85/02 ; H05K3/06

Abstract:
A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.
Public/Granted literature
- US20200043690A1 MULTILAYER PRINTED CIRCUIT BOARD VIA HOLE REGISTRATION AND ACCURACY Public/Granted day:2020-02-06
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