Invention Grant
- Patent Title: Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices
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Application No.: US16465039Application Date: 2016-12-29
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Publication No.: US10886272B2Publication Date: 2021-01-05
- Inventor: Stephen M. Cea , Rishabh Mehandru , Anupama Bowonder , Anand S. Murthy , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- International Application: PCT/US2016/069126 WO 20161229
- International Announcement: WO2018/125120 WO 20180705
- Main IPC: H01L29/165
- IPC: H01L29/165 ; H01L29/78 ; H01L29/66 ; H01L27/092 ; H01L21/02 ; H01L21/8238 ; H01L29/06

Abstract:
Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.
Public/Granted literature
- US20190326290A1 TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND P-MOS DEVICES Public/Granted day:2019-10-24
Information query
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