Invention Grant
- Patent Title: Vertical field effect transistor with reduced gate to source/drain capacitance
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Application No.: US16455045Application Date: 2019-06-27
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Publication No.: US10892324B2Publication Date: 2021-01-12
- Inventor: Juntao Li , Kangguo Cheng , Choonghyun Lee , Peng Xu
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Randall Bluestone
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/08 ; H01L29/78

Abstract:
A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin layer on a bottom source/drain layer, and forming one or more fin templates on the vertical fin layer. The method further includes forming a vertical fin below each of the one or more fin templates. The method further includes reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.
Public/Granted literature
- US20190386101A1 VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE Public/Granted day:2019-12-19
Information query
IPC分类: