Invention Grant
- Patent Title: Methods of forming metal silicide layers and metal silicide layers formed therefrom
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Application No.: US16366539Application Date: 2019-03-27
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Publication No.: US10916433B2Publication Date: 2021-02-09
- Inventor: He Ren , Maximillian Clemons , Mei-Yee Shek , Minrui Yu , Bencherki Mebarki , Mehul B. Naik , Chentsau Ying , Srinivas D. Nemani
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Main IPC: H01L21/285
- IPC: H01L21/285 ; H01L21/32 ; H01L21/768 ; C23C14/04 ; C23C14/06 ; C23C14/35 ; C23C14/22 ; C23C14/58 ; H01L29/45 ; H01L21/3205 ; H01L23/532

Abstract:
Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.
Public/Granted literature
- US20190311908A1 METHODS OF FORMING METAL SILICIDE LAYERS AND METAL SILICIDE LAYERS FORMED THEREFROM Public/Granted day:2019-10-10
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