公开(公告)号：US12201030B2

公开(公告)日：2025-01-14

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui Yu ,  Wenhui Wang ,  Jaesoo Ahn ,  Jong Mun Kim ,  Sahil Patel ,  Lin Xue ,  Chando Park ,  Mahendra Pakala ,  Chentsau Chris Ying ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US10685849B1

公开(公告)日：2020-06-16

申请号：US16400737

申请日：2019-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US11965236B2

公开(公告)日：2024-04-23

申请号：US16511627

申请日：2019-07-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Minrui Yu ,  He Ren ,  Mehul Naik

IPC: C23C14/56 ,  C23C14/06 ,  C23C14/54 ,  C23C14/58 ,  H01J37/34 ,  H01L21/285

CPC classification number: C23C14/0682 ,  C23C14/542 ,  C23C14/56 ,  C23C14/5806 ,  H01J37/3429 ,  H01L21/28556

Abstract: Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.

公开(公告)号：US11289342B2

公开(公告)日：2022-03-29

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US10916433B2

公开(公告)日：2021-02-09

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Maximillian Clemons ,  Mei-Yee Shek ,  Minrui Yu ,  Bencherki Mebarki ,  Mehul B. Naik ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/285 ,  H01L21/32 ,  H01L21/768 ,  C23C14/04 ,  C23C14/06 ,  C23C14/35 ,  C23C14/22 ,  C23C14/58 ,  H01L29/45 ,  H01L21/3205 ,  H01L23/532

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US10388533B2

公开(公告)日：2019-08-20

申请号：US15988854

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Minrui Yu ,  Mehul B. Naik

IPC: H01L23/40 ,  H01L21/285 ,  H01L21/67 ,  H01L23/532 ,  H01L21/768 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01J37/34

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

公开(公告)号：US20240306391A1

公开(公告)日：2024-09-12

申请号：US18597057

申请日：2024-03-06

Applicant: Applied Materials, Inc.

Inventor： Hao-Ling Tang ,  Arvind Kumar ,  Mahendra Pakala ,  Keith Tatseun Wong ,  Yi-Hsuan Hsiao ,  Dongqing Yang ,  Mark Conrad ,  Rio Soedibyo ,  Minrui Yu

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Two-dimensional (2D) materials formed in very thin layers improve the operation of semiconductor devices. However, forming a contact on 2D material tends to damage and penetrate the 2D material. A relatively gentle etch process has been developed that is very selective to the 2D material and allows vertical holes to be etched down to the 2D material without damaging or penetrating the 2D material. A low-power deposition process forms a protective liner when performing the metal fill to further prevent damage to the 2D material when forming the metal contacts in the holes. These processes allow a vertical metal contact to be formed on a planar 2D material or a vertical sidewall contact be formed in a 3D NAND without damaging the 2D material. This increases the contact area, reduces the contact resistance, and improves the performance of the 2D material in the device.

公开(公告)号：US11723283B2

公开(公告)日：2023-08-08

申请号：US16871779

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Minrui Yu ,  Wenhui Wang ,  Jaesoo Ahn ,  Jong Mun Kim ,  Sahil Patel ,  Lin Xue ,  Chando Park ,  Mahendra Pakala ,  Chentsau Chris Ying ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/095 ,  G01R33/098 ,  G11C11/161 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US11145808B2

公开(公告)日：2021-10-12

申请号：US16681351

申请日：2019-11-12

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Minrui Yu ,  Chando Park ,  Mang-Mang Ling ,  Jaesoo Ahn ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Mahendra Pakala ,  Ellie Y. Yieh

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

公开(公告)号：US20200350178A1

公开(公告)日：2020-11-05

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.