- Patent Title: Peripheral component interconnect express (PCIE) network with input/output (I/O) operation chaining to reduce communication time within execution of I/O channel operations
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Application No.: US16682481Application Date: 2019-11-13
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Publication No.: US10949097B2Publication Date: 2021-03-16
- Inventor: Edward W. Chencinski , Bruce Ratcliff , Eric N. Lais , Michael James Becht , Matthias Klein
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Steven Chiu, Esq.; Blanche E. Schiller, Esq.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F13/16 ; G06F13/42
Abstract:
A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
Public/Granted literature
- US20200081627A1 I/O OPERATION CHAINING TO REDUCE COMMUNICATION TIME WITHIN EXECUTION OF I/O CHANNEL OPERATIONS Public/Granted day:2020-03-12
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