A semiconductor device 50 of the invention includes a supply voltage VCC, a plurality of registers 14, a PMOS transistor P, an AND gate 12, and a determination circuit 16. The registers 14 include a first register and a second register. The first register can keep data, and the second register can keep a check bit. The PMOS transistor P and the AND gate 12 are both connected between the supply voltage VCC and the registers 14, and both control the supply from the supply voltage VCC to the registers 14. The determination circuit 16 determines whether the check bit kept in the second register is correct or not in a DPD (deep-power-down) mode. An operating margin of the second register is worse than that of the first register. While the determination circuit 16 determines that the check bit kept in the second register is incorrect, the PMOS transistor P provides the supply voltage VCC to the registers 14.