Invention Grant
- Patent Title: Resistor between gates in self-aligned gate edge architecture
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Application No.: US16474896Application Date: 2017-03-31
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Publication No.: US10964690B2Publication Date: 2021-03-30
- Inventor: Roman W. Olac-Vaw , Walid M. Hafez , Chia-Hong Jan , Hsu-Yu Chang , Neville L. Dias , Rahul Ramaswamy , Nidhi Nidhi , Chen-Guan Lee
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/025589 WO 20170331
- International Announcement: WO2018/182736 WO 20181004
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L49/02

Abstract:
Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
Public/Granted literature
- US20200043914A1 RESISTOR BETWEEN GATES IN SELF-ALIGNED GATE EDGE ARCHITECTURE Public/Granted day:2020-02-06
Information query
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