A signal processor is provided, comprising a data variable delay circuit that delays data signals, a clock variable delay circuit that delays a clock signal indicating timing to acquire the data signals, a jitter signal supplying unit that supplies, to the data variable delay circuit and the clock variable delay circuit, a jitter signal to change an amount of delay in a same direction, and a re-timing circuit that outputs a jitter-applied data signal obtained by re-timing the data signals delayed by the data variable delay circuit with the clock signal delayed by the clock variable delay circuit.