公开(公告)号：US20250076367A1

公开(公告)日：2025-03-06

申请号：US18817872

申请日：2024-08-28

Applicant: ADVANTEST Corporation

Inventor： Aritomo Kikuchi ,  Toshiyuki Kiyokawa

IPC: G01R31/28

Abstract: A semiconductor wafer handling apparatus moves a semiconductor wafer including a first surface on which a terminal of one or more device under tests (DUTs) is disposed and presses the terminal against a contactor of a probe card. The semiconductor wafer handling apparatus includes: a holder that holds the semiconductor wafer such that the first surface and a second surface of the semiconductor wafer are at least partially exposed; a first moving device that relatively moves the holder with respect to the probe card; a temperature adjusting device that contacts the second surface of the semiconductor wafer and adjusts a temperature of the DUTs; and a second moving device that relatively moves the temperature adjusting device with respect to the semiconductor wafer held by the holder.

公开(公告)号：US20250076366A1

公开(公告)日：2025-03-06

申请号：US18816814

申请日：2024-08-27

Applicant: ADVANTEST Corporation

Inventor： Aritomo Kikuchi ,  Toshiyuki Kiyokawa

IPC: G01R31/28 ,  G01R1/073

Abstract: A semiconductor wafer handling apparatus that moves a semiconductor wafer including a device under test (DUT) and presses a terminal of the DUT against a contactor of a probe card, the semiconductor wafer handling apparatus includes an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT. The terminal is disposed on a first surface of the semiconductor wafer. The optical connection part is disposed on a second surface of the semiconductor wafer.

公开(公告)号：US12241926B2

公开(公告)日：2025-03-04

申请号：US17512021

申请日：2021-10-27

Applicant: ADVANTEST CORPORATION ,  TOEI SCIENTIFIC INDUSTRIAL CO., LTD.

Inventor： Naoyoshi Watanabe ,  Shigeyuki Sato ,  Ryoichi Utsumi

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  G01R31/28

Abstract: A test apparatus tests a wafer under test on which devices under test each including magnetoresistive memory or a magnetic sensor are formed. In a test process, the wafer under test is mounted on a stage. In the test process, a magnetic field application apparatus applies a magnetic field BEX to the wafer under test. A test probe card is used in the test process. Multiple magnetization detection units are formed on a diagnostic wafer. In a diagnostic process of the test apparatus, the diagnostic wafer is mounted on the stage instead of the wafer under test. Each magnetization detection unit is capable of measuring a magnetic field BEX generated by the magnetic field application apparatus. In the diagnostic process, the diagnostic probe card is used instead of the test probe card.

公开(公告)号：US12216559B2

公开(公告)日：2025-02-04

申请号：US18139262

申请日：2023-04-25

Applicant: Advantest Corporation

Inventor： Srdjan Malisic ,  Chi Yuan

IPC: G06F11/27 ,  G06F11/00 ,  G06F12/00 ,  G06F12/02

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

公开(公告)号：US20250031455A1

公开(公告)日：2025-01-23

申请号：US18908714

申请日：2024-10-07

Applicant: ADVANTEST CORPORATION ,  ISTITUTE OF SCIENCE TOKYO

Inventor： Shinji SUGATANI ,  Takayuki OHBA

IPC: H01L27/06 ,  G11C29/12 ,  H01L21/50 ,  H01L21/66 ,  H01L23/538 ,  H01L25/065

Abstract: When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

公开(公告)号：US12197303B2

公开(公告)日：2025-01-14

申请号：US18129414

申请日：2023-03-31

Applicant: ADVANTEST CORPORATION

Inventor： Srdjan Malisic ,  Chi Yuan

IPC: G06F11/263 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273 ,  G06F21/53

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing flexible and independent parallel testing across the plurality of DUTs. In one exemplary implementation, the tester generates and manages workloads independently for DUTs included in the plurality of DUTs. The DUTs can be memory devices the tester is configured to test different memory spaces in parallel. The different memory spaces can have various implementations (e.g., included in the plurality of DUTs, different memory spaces are within one of the DUTs included in the plurality of DUTs, etc.). Workloads can be generated based upon individual characteristics of the DUTS and managed separately. The testing can include performance testing. (e.g., bandwidth testing, latency testing, error testing, etc.).

公开(公告)号：US12176591B2

公开(公告)日：2024-12-24

申请号：US17721939

申请日：2022-04-15

Applicant: Advantest Corporation

Inventor： Giovanni Bianchi

IPC: H01P1/203 ,  H01P1/201 ,  H01P7/08

Abstract: An electrical filter structure for forwarding an electrical signal from a first port, e.g. P1, to a second port, e.g. P2, in a frequency selective manner, wherein the filter is a microwave filter, the electrical filter structure comprising: a plurality of pairs of an open stub and a short-circuited stub coupled electrically in parallel to a transmission line comprising a plurality of transmission line portions at a plurality of respective junctions between adjacent transmission line portions, e.g. Cross junction; and wherein the first port is connected with a first of the junctions having a first pair comprising a first open stub and a first short-circuited stub; wherein the second port is connected with a last of the junctions having a last pair comprising a last open stub and a last short-circuited stub; wherein lengths of the pair of the open stub and the short-circuited stub coupled to a same of the junctions are chosen such that electrical lengths of the open stub and short-circuited stub of the respective pairs are equal within a tolerance of +/−10%.

公开(公告)号：US20240393389A1

公开(公告)日：2024-11-28

申请号：US18753303

申请日：2024-06-25

Applicant: ADVANTEST CORPORATION

Inventor： Kosuke IKEDA ,  Hajime SUGIMURA

IPC: G01R31/28

Abstract: A condition data acquirer acquires first data (condition data) of a plurality of items related to a test process of a plurality of semiconductor chips. A test result acquirer acquires second data (test result data) indicating test results of the plurality of semiconductor chips in the test process. A decision tree generator generates a decision tree with each item of the condition data as a feature amount and the test result data as a target value. An analysis result outputter outputs, as an item having a large influence on the test results, information of a feature amount having a relatively high importance in the decision tree.

公开(公告)号：US20240393383A1

公开(公告)日：2024-11-28

申请号：US18753355

申请日：2024-06-25

Applicant: ADVANTEST CORPORATION

Inventor： Kosuke IKEDA ,  Tatsuaki GUNYA

IPC: G01R31/26

Abstract: A condition data acquirer acquires first data of a plurality of items related to a test process of a plurality of semiconductor chips. A test result acquirer acquires second data indicating test results of the plurality of semiconductor chips in the test process. In a region in which a plurality of items of the condition data are arranged on one axis and a plurality of values of the respective items is arranged in a direction orthogonal to the axis, a graph generator generates a graph image in which corresponding values are connected by lines over the plurality of items for each group of a plurality of semiconductor chips having the same test environment. The graph generator changes a form of the lines for each group in the graph image according to a ratio of the semiconductor chips whose test results have been failed in each group.

公开(公告)号：US12140610B2

公开(公告)日：2024-11-12

申请号：US17484355

申请日：2021-09-24

Applicant: ADVANTEST Corporation

Inventor： Toshiyuki Kiyokawa ,  Kazuya Ohtani

IPC: G01R1/04

Abstract: A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT; and a lid member that covers the DUT and is attached to the carrier body. The lid member includes a through-hole for sucking the DUT that is provided to face the DUT and penetrating through the lid member.