Invention Grant
- Patent Title: Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability
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Application No.: US16324479Application Date: 2016-09-30
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Publication No.: US11011537B2Publication Date: 2021-05-18
- Inventor: Aaron D. Lilak , Patrick Theofanis , Patrick Morrow , Rishabh Mehandru , Stephen M. Cea
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- International Application: PCT/US2016/055012 WO 20160930
- International Announcement: WO2018/063396 WO 20180405
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11575 ; H01L27/1157
Abstract:
An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polymer with an electrically conductive material.
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Information query
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