Invention Grant
- Patent Title: Techniques for increasing channel region tensile strain in n-MOS devices
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Application No.: US16322815Application Date: 2016-09-27
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Publication No.: US11011620B2Publication Date: 2021-05-18
- Inventor: Rishabh Mehandru , Cory E. Weber , Anand S. Murthy , Karthik Jambunathan , Glenn A. Glass , Jiong Zhang , Ritesh Jhaveri , Szuya S. Liao
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/054022 WO 20160927
- International Announcement: WO2018/063166 WO 20180405
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/66 ; H01L21/8238 ; H01L29/78 ; H01L29/32

Abstract:
Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.
Public/Granted literature
- US20190207015A1 TECHNIQUES FOR INCREASING CHANNEL REGION TENSILE STRAIN IN N-MOS DEVICES Public/Granted day:2019-07-04
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