Invention Grant
- Patent Title: Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal
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Application No.: US16665179Application Date: 2019-10-28
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Publication No.: US11022639B2Publication Date: 2021-06-01
- Inventor: Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G01R29/26
- IPC: G01R29/26 ; G01R31/317
Abstract:
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
Information query
