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    Receiver with enhanced clock and data recovery
    2.
    发明申请
    Receiver with enhanced clock and data recovery 审中-公开

    公开(公告)号：US20200052873A1

    公开(公告)日：2020-02-13

    申请号：US16549303

    申请日：2019-08-23

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Brian Leibowitz ,  Jaeha Kim ,  Jafar Savoj

    IPC: H04L7/00 ,  H04L7/033 ,  G06Q10/10 ,  G06Q10/06 ,  H04L25/06

    Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

    Data Transmission Using Delayed Timing Signals
    4.
    发明申请
    Data Transmission Using Delayed Timing Signals 有权

    公开(公告)号：US20230073567A1

    公开(公告)日：2023-03-09

    申请号：US17883345

    申请日：2022-08-08

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Receiver with enhanced clock and data recovery
    5.
    发明申请
    Receiver with enhanced clock and data recovery 有权

    公开(公告)号：US20210152324A1

    公开(公告)日：2021-05-20

    申请号：US17114348

    申请日：2020-12-07

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Brian Leibowitz ,  Jaeha Kim ,  Jafar Savoj

    IPC: H04L7/00 ,  H04L25/06 ,  G06Q10/06 ,  G06Q10/10 ,  H04L7/033

    Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

    Clock and Data Recovery Having Shared Clock Generator
    7.
    发明申请
    Clock and Data Recovery Having Shared Clock Generator 审中-公开

    公开(公告)号：US20190007189A1

    公开(公告)日：2019-01-03

    申请号：US16032616

    申请日：2018-07-11

    Applicant: Rambus Inc.

    Inventor： Masum HOSSAIN ,  Brian Leibowitz ,  Jihong Ren

    IPC: H04L7/00 ,  H03L7/23 ,  H04L7/033 ,  H04L27/00 ,  H04L27/32 ,  H03L7/197

    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

    Decision Feedback Equalizer
    9.
    发明申请
    Decision Feedback Equalizer 有权
    决策反馈均衡器

    公开(公告)号：US20160134442A1

    公开(公告)日：2016-05-12

    申请号：US14938163

    申请日：2015-11-11

    Applicant: Rambus Inc.

    Inventor： Brian Leibowitz ,  Jaeha Kim

    IPC: H04L25/03 ,  H03M1/12

    CPC classification number: H04L25/03057 ,  H03M1/004 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/362 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/03363 ,  H04L2025/03369

    Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

    Abstract translation: 在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。 在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。 当前解析的位然后被存储为最近以前解析的位，以准备下一个符号时间。 选择逻辑可以是可编程的，以适应过程，环境和系统变化。

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