Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.