Invention Grant
- Patent Title: Reliability in start up sequence for D-mode power FET driver
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Application No.: US16992003Application Date: 2020-08-12
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Publication No.: US11057031B1Publication Date: 2021-07-06
- Inventor: Arezu Bagheri , Buddhika Abesingha , Ronald E. Reedy
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Steinfl + Bruno LLP
- Main IPC: H02M1/36
- IPC: H02M1/36 ; H03K17/22 ; H02M3/07 ; H02M1/08 ; H03K17/06

Abstract:
Methods and devices to address start up of half-bridge circuits including D-mode power FETs are disclosed. The disclosed devices overcome possible issues of output overload or excess current through gate-source of power FETs during start up. Methods and devices based on monitoring coupling capacitors voltages and pre-charging such coupling capacitors using current sources are also described. The current sources can be implemented using negative voltages provided by negative voltage sources such as charge pumps.
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