Invention Grant
- Patent Title: Dual processor power saving architecture communications system
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Application No.: US17006811Application Date: 2020-08-29
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Publication No.: US11112847B2Publication Date: 2021-09-07
- Inventor: Partha Sarathy Murali , Subba Reddy Kallam , Venkat Mattela
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: File-EE-Patents.com
- Agent Jay A. Chesavage
- Main IPC: G06F1/3228
- IPC: G06F1/3228 ; G06F1/3234 ; G06F9/54 ; H04L29/12 ; H04W4/12 ; H04W4/80 ; H04L12/58 ; G06F9/445 ; H04B1/00 ; H04B1/04

Abstract:
A communications system has a low power connectivity processor and a high performance applications processor. The low power connectivity processor is coupled to a low power front end for wireless packets and the high performance applications processor is coupled to a high performance front end. A power controller is coupled to the low power front end and enables the applications processor and high performance front end when wireless packets which require greater processing capacity are received, and removes power from the applications processor and high performance front end at other times.
Public/Granted literature
- US20210075451A1 Dual Processor Power Saving Architecture Communications System Public/Granted day:2021-03-11
Information query
IPC分类: