Invention Grant
- Patent Title: Package architecture with improved via drill process and method for forming such package
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Application No.: US16017393Application Date: 2018-06-25
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Publication No.: US11177234B2Publication Date: 2021-11-16
- Inventor: Suddhasattwa Nad , Rahul Manepalli , Marcel Wall
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/29
- IPC: H01L23/29 ; H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L23/532

Abstract:
Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.
Public/Granted literature
- US20190393183A1 PACKAGE ARCHITECTURE WITH IMPROVED VIA DRILL PROCESS AND METHOD FOR FORMING SUCH PACKAGE Public/Granted day:2019-12-26
Information query
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