Invention Grant
- Patent Title: Inner spacer for nanosheet transistors
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Application No.: US16680633Application Date: 2019-11-12
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Publication No.: US11195912B2Publication Date: 2021-12-07
- Inventor: Kangguo Cheng , Choonghyun Lee , Juntao Li , Peng Xu
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Erik Johnson
- Main IPC: H01L29/41
- IPC: H01L29/41 ; H01L29/06 ; H01L29/423 ; H01L29/78 ; H01L21/02 ; H01L29/66 ; H01L29/775 ; H01L29/786 ; B82Y10/00

Abstract:
A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.
Public/Granted literature
- US20200098860A1 INNER SPACER FOR NANOSHEET TRANSISTORS Public/Granted day:2020-03-26
Information query
IPC分类: