Invention Grant
- Patent Title: Method of manufacturing wafer level low melting temperature interconnections
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Application No.: US16675992Application Date: 2019-11-06
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Publication No.: US11222813B2Publication Date: 2022-01-11
- Inventor: Sean P. Kilcoyne , Eric R. Miller , George Grama
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Burns & Levinson, LLP
- Agent Joseph M. Maraia
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/56 ; H05K3/42 ; C23C18/16 ; H01L23/31 ; H01L23/528 ; C25D7/12 ; H01L21/02 ; H01L23/00
Abstract:
A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.
Public/Granted literature
- US20200075396A1 METHOD OF MANUFACTURING WAFER LEVEL LOW MELTING TEMPERATURE INTERCONNECTIONS Public/Granted day:2020-03-05
Information query
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