公开(公告)号：US11753736B2

公开(公告)日：2023-09-12

申请号：US17098560

申请日：2020-11-16

Applicant: Raytheon Company

Inventor： Michael J. Rondon ,  Jon Sigurdson ,  Eric R. Miller

IPC: C25D7/12 ,  C23C14/18 ,  C25D3/54

CPC classification number: C25D7/12 ,  C23C14/18 ,  C25D3/54

Abstract: A method for fabricating a wafer stack. The method includes forming a tantalum-nitride film on a substrate of the wafer stack using physical vapor deposition, forming a tantalum layer on the tantalum-nitride film using physical vapor deposition, and depositing indium on the tantalum layer using electroplating.

公开(公告)号：US20220359437A1

公开(公告)日：2022-11-10

申请号：US17871215

申请日：2022-07-22

Applicant: Raytheon Company

Inventor： Eric R. Miller ,  Sean P. Kilcoyne ,  Michael V. Liguori ,  Michael J. Rondon

IPC: H01L23/00 ,  H01L21/66

Abstract: Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

公开(公告)号：US20190252244A1

公开(公告)日：2019-08-15

申请号：US15895512

申请日：2018-02-13

Applicant: Raytheon Company

Inventor： Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC: H01L21/768 ,  H01L21/56 ,  H05K3/42 ,  C23C18/16 ,  H01L23/31 ,  H01L23/528 ,  C25D7/12

CPC classification number: H01L21/7684 ,  C23C18/1653 ,  C23C18/168 ,  C25D7/123 ,  H01L21/02065 ,  H01L21/568 ,  H01L21/76873 ,  H01L23/3121 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L2221/1089 ,  H01L2224/03009 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83896 ,  H05K3/424

Abstract: A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

公开(公告)号：US20240018684A1

公开(公告)日：2024-01-18

申请号：US18363998

申请日：2023-08-02

Applicant: Raytheon Company

Inventor： Michael J. Rondon ,  Jon Sigurdson ,  Eric R. Miller

IPC: C25D7/12 ,  C23C14/18 ,  C25D3/54

CPC classification number: C25D7/12 ,  C23C14/18 ,  C25D3/54

Abstract: A wafer stack can be produced by using indium electroplating on physical vapor deposition tantalum. The wafer stack includes a substrate, a tantalum-nitride film formed on the substrate, a tantalum layer formed on the tantalum-nitride film, and indium deposited on the tantalum layer. Various relationships of thicknesses between the tantalum layer and the tantalum-nitride film can be used in producing the wafer stack.

公开(公告)号：US20220013478A1

公开(公告)日：2022-01-13

申请号：US16923332

申请日：2020-07-08

Applicant: Raytheon Company

Inventor： Eric R. Miller ,  Sean P. Kilcoyne ,  Michael V. Liguori ,  Michael J. Rondon

IPC: H01L23/00 ,  H01L21/66

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

公开(公告)号：US10515837B2

公开(公告)日：2019-12-24

申请号：US15945341

申请日：2018-04-04

Applicant: Raytheon Company

Inventor： Sean P. Kilcoyne ,  Eric R. Miller

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/306 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

Abstract: Methods, assemblies, and equipment are described for bonding one or more die that may be of dissimilar thickness to a wafer. The die may be fabricated and singulated with a planarized oxide layer protecting from wafer dicing and handling debris one or more metallized post structures connecting to an integrated circuit. Face sides of the die are bonded to a first handle wafer, such that the respective post structures are aligned in a common plane. The substrate material back sides of the bonded die are then thinned to a uniform thickness and bonded to a second handle wafer. The assembly may then be flipped, and the first handle wafer and protective layer including potential dicing and handling debris removed. The post structures are revealed, resulting in a composite wafer assembly including the second handle and one or more uniformly thinned die mounted thereto.

公开(公告)号：US12148721B2

公开(公告)日：2024-11-19

申请号：US17871215

申请日：2022-07-22

Applicant: Raytheon Company

Inventor： Eric R. Miller ,  Sean P. Kilcoyne ,  Michael V. Liguori ,  Michael J. Rondon

IPC: H01L23/00 ,  H01L21/66

Abstract: Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

公开(公告)号：US20220157881A1

公开(公告)日：2022-05-19

申请号：US16952783

申请日：2020-11-19

Applicant: RAYTHEON COMPANY

Inventor： Jamal I. Mustafa ,  Robert C. Anderson ,  John L. Vampola ,  Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC: H01L27/146

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

公开(公告)号：US11222813B2

公开(公告)日：2022-01-11

申请号：US16675992

申请日：2019-11-06

Applicant: Raytheon Company

Inventor： Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC: H01L21/768 ,  H01L21/56 ,  H05K3/42 ,  C23C18/16 ,  H01L23/31 ,  H01L23/528 ,  C25D7/12 ,  H01L21/02 ,  H01L23/00

Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

公开(公告)号：US20200075396A1

公开(公告)日：2020-03-05

申请号：US16675992

申请日：2019-11-06

Applicant: Raytheon Company

Inventor： Sean P. Kilcoyne ,  Eric R. Miller ,  George Grama

IPC: H01L21/768 ,  H01L21/56 ,  H05K3/42 ,  C23C18/16 ,  H01L23/31 ,  H01L23/528 ,  C25D7/12 ,  H01L21/02 ,  H01L23/00

Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.