Invention Grant
- Patent Title: Semiconductor package having enlarged gate pad and method of making the same
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Application No.: US16906384Application Date: 2020-06-19
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Publication No.: US11222858B1Publication Date: 2022-01-11
- Inventor: Yan Xun Xue , Yueh-Se Ho , Long-Ching Wang , Xiaotian Zhang , Zhiqiang Niu
- Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
- Applicant Address: US CA Sunnyvale
- Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
- Current Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
- Current Assignee Address: US CA Sunnyvale
- Agent Chen-Chi Lin
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L23/00 ; H01L23/31 ; H01L23/495

Abstract:
A semiconductor package fabrication method comprises the steps of providing a wafer, applying a seed layer, forming a photo resist layer, plating a copper layer, removing the photo resist layer, removing the seed layer, applying a grinding process, forming metallization, and applying a singulation process. A semiconductor package comprises a silicon layer, an aluminum layer, a passivation layer, a polyimide layer, a copper layer, and metallization. In one example, an area of a contact area of a gate clip is smaller than an area of a gate copper surface. The area of the contact area of the gate clip is larger than a gate aluminum surface. In another example, an area of a contact area of a gate pin is larger than an area of a gate copper surface. The area of the contact area of the gate pin is larger than a gate aluminum surface.
Public/Granted literature
- US20210398926A1 SEMICONDUCTOR PACKAGE HAVING ENLARGED GATE PAD AND METHOD OF MAKING THE SAME Public/Granted day:2021-12-23
Information query
IPC分类: