公开(公告)号：US20250118638A1

公开(公告)日：2025-04-10

申请号：US18378503

申请日：2023-10-10

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Jian Yin ,  Lin Chen ,  Ziwei Yu ,  Xiaobin Wang ,  Zhiqiang Niu ,  Kuan-Hung Li

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.

公开(公告)号：US20250112132A1

公开(公告)日：2025-04-03

申请号：US18375388

申请日：2023-09-29

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Zhiqiang Niu ,  Xiao Zhang ,  Long-Ching Wang ,  Guobing Shen ,  Yan Xun Xue

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises a top plate, a plurality of drain pads, a plurality of slanted sections, a gate pad, and a plurality of source pads. The top plate of the lead frame comprises a thicker region and a thinner region. Each slanted section of the plurality of slanted sections connects a respective drain pad of the plurality of drain pads to the top plate. A respective side surface of each drain pad of the plurality of drain pads is exposed from a side surface of the molding encapsulation. A respective bottom surface of each drain pad of the plurality of drain pads is exposed from a bottom surface of the molding encapsulation. A top surface of the thicker region is exposed from a top surface of the molding encapsulation.

公开(公告)号：US20250096081A1

公开(公告)日：2025-03-20

申请号：US18368557

申请日：2023-09-14

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Madhur Bobde ,  Yan Xun Xue ,  Long-Ching Wang ,  Jian Yin ,  Sitthipong Angkititrakul

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: A semiconductor package comprising a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, an interposer, an integrated circuit (IC) controller, and a molding encapsulation. A method, for fabricating a semiconductor package, comprises the steps of: providing a lead frame; attaching a low side FET and a high side FET; mounting a metal clip; attaching an interposer; mounting an IC controller, forming a molding encapsulation; and applying a singulation process.

公开(公告)号：US20230215783A1

公开(公告)日：2023-07-06

申请号：US17566294

申请日：2021-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Long-Ching Wang ,  Xiaoguang Zeng ,  Mary Jane R. Alin ,  Hailin Zhou ,  Guobing Shen

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L23/49541 ,  H01L23/3107 ,  H01L24/40 ,  H01L2224/40175

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

公开(公告)号：US20250070049A1

公开(公告)日：2025-02-27

申请号：US18882783

申请日：2024-09-12

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Lin Lv ,  Zhen Yang ,  Shuhua Zhou ,  Long-Ching Wang

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/78

Abstract: A semiconductor package comprises a semiconductor substrate, a plurality of contact pads, a seed layer, a first thick metal layer, a second thick metal layer, and a coating metal layer. Direct attachment of the first thick metal layer and the second thick metal layer comprises bonded metal atoms. The first thick metal layer and the second thick metal layer are bonded by an SAB process. A method comprises the steps of providing an upper device portion, providing a lower carrier portion, applying an SAB process, applying a de-bonding process, applying a tape, applying a singulation process, and removing the tape.

公开(公告)号：US12142548B2

公开(公告)日：2024-11-12

申请号：US17566294

申请日：2021-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Long-Ching Wang ,  Xiaoguang Zeng ,  Mary Jane R. Alin ,  Hailin Zhou ,  Guobing Shen

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

公开(公告)号：US20230021687A1

公开(公告)日：2023-01-26

申请号：US17960700

申请日：2022-10-05

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Jun Lu ,  Long-Ching Wang ,  Madhur Bobde ,  Bo Chen ,  Shuhua Zhou

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L23/15

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

公开(公告)号：US11495548B2

公开(公告)日：2022-11-08

申请号：US17137893

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Jun Lu ,  Long-Ching Wang ,  Madhur Bobde ,  Bo Chen ,  Shuhua Zhou

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/15

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.

公开(公告)号：US11430762B2

公开(公告)日：2022-08-30

申请号：US17137811

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/78

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.

公开(公告)号：US20220208724A1

公开(公告)日：2022-06-30

申请号：US17137811

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.