Invention Grant
- Patent Title: Method and apparatus to improve write bandwidth of a block-based multi-level cell nonvolatile memory
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Application No.: US16532996Application Date: 2019-08-06
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Publication No.: US11237732B2Publication Date: 2022-02-01
- Inventor: Shankar Natarajan , Suresh Nagarajan , Yihua Zhang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law, PC
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G11C11/56 ; G11C16/04

Abstract:
Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.
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