公开(公告)号：US12147286B2

公开(公告)日：2024-11-19

申请号：US17129116

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Anoop Mukker ,  Romesh Trivedi ,  Suresh Nagarajan

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/3221 ,  G06F1/3234

Abstract: Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

公开(公告)号：US11783893B2

公开(公告)日：2023-10-10

申请号：US17133459

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Aliasgar S. Madraswala ,  Yihua Zhang

IPC: G11C7/10 ,  G11C11/56 ,  G11C29/42

CPC classification number: G11C11/5628 ,  G11C7/1039 ,  G11C11/5642 ,  G11C29/42

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

公开(公告)号：US20220004495A1

公开(公告)日：2022-01-06

申请号：US17475984

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Chace Clark ,  Francis Corrado ,  Shivashekar Muralishankar ,  Suresh Nagarajan

IPC: G06F12/0802 ,  G06F3/06

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

公开(公告)号：US11237732B2

公开(公告)日：2022-02-01

申请号：US16532996

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Yihua Zhang

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04

Abstract: Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.

公开(公告)号：US10996860B2

公开(公告)日：2021-05-04

申请号：US16176465

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Shankar Natarajan

IPC: G06F3/06

Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.

公开(公告)号：US20190267080A1

公开(公告)日：2019-08-29

申请号：US16288268

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Sriram Natarajan ,  Suresh Nagarajan ,  Ramkarthik Ganesan ,  Arun S. Athreya ,  Romesh B. Trivedi

IPC: G11C11/56 ,  G11C16/20 ,  G06F12/06 ,  G11C16/16

Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

公开(公告)号：US11769557B2

公开(公告)日：2023-09-26

申请号：US16715791

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Arun Sitaram Athreya ,  Shankar Natarajan ,  Sriram Natarajan ,  Yihua Zhang ,  Suresh Nagarajan

IPC: G11C16/04 ,  G11C16/34 ,  G06F3/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

公开(公告)号：US11119672B2

公开(公告)日：2021-09-14

申请号：US16532870

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Shivashekar Muralishankar ,  Sriram Natarajan ,  Yihua Zhang

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G06F12/02

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

公开(公告)号：US20200167089A1

公开(公告)日：2020-05-28

申请号：US16532870

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Shivashekar Muralishankar ,  Sriram Natarajan ,  Yihua Zhang

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

公开(公告)号：US10229735B1

公开(公告)日：2019-03-12

申请号：US15852928

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Sriram Natarajan ,  Suresh Nagarajan ,  Ramkarthik Ganesan ,  Arun S. Athreya ,  Romesh B. Trivedi

IPC: G06F12/06 ,  G11C11/56 ,  G11C16/16 ,  G11C16/20

Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.