Invention Grant
- Patent Title: Monolithic chip stacking using a die with double-sided interconnect layers
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Application No.: US16633543Application Date: 2017-09-25
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Publication No.: US11251158B2Publication Date: 2022-02-15
- Inventor: Anup Pancholi , Kimin Jun
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- International Application: PCT/US2017/053291 WO 20170925
- International Announcement: WO2019/059950 WO 20190328
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/56 ; H01L21/683 ; H01L23/00 ; H01L25/00
Abstract:
An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
Public/Granted literature
- US20200212011A1 MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT LAYERS Public/Granted day:2020-07-02
Information query
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