Invention Grant
- Patent Title: Power management for partial cache line information storage between memories
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Application No.: US16651496Application Date: 2017-11-21
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Publication No.: US11281277B2Publication Date: 2022-03-22
- Inventor: Yingwen Chen , Tao Xu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- International Application: PCT/CN2017/112007 WO 20171121
- International Announcement: WO2019/100186 WO 20190531
- Main IPC: G06F1/30
- IPC: G06F1/30 ; G06F1/3234 ; G06F11/30 ; G06F12/0895 ; G06F13/16
Abstract:
An embodiment of a semiconductor package apparatus may include technology to store cache line spare information in a first memory, detect a first power state change for the first memory, and save the cache line spare information to a second memory based on the detected first power state change. Other embodiments are disclosed and claimed.
Public/Granted literature
- US20200264681A1 POWER MANAGEMENT FOR PARTIAL CACHE LINE SPARING Public/Granted day:2020-08-20
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