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公开(公告)号:US11481294B2
公开(公告)日:2022-10-25
申请号:US17262696
申请日:2018-09-15
Applicant: INTEL CORPORATION
Inventor: Satish Muthiyalu , Yingwen Chen , Yu Yu , Tao Xu
Abstract: Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.
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公开(公告)号:US11281277B2
公开(公告)日:2022-03-22
申请号:US16651496
申请日:2017-11-21
Applicant: Intel Corporation
Inventor: Yingwen Chen , Tao Xu
IPC: G06F1/30 , G06F1/3234 , G06F11/30 , G06F12/0895 , G06F13/16
Abstract: An embodiment of a semiconductor package apparatus may include technology to store cache line spare information in a first memory, detect a first power state change for the first memory, and save the cache line spare information to a second memory based on the detected first power state change. Other embodiments are disclosed and claimed.
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公开(公告)号:US12169460B2
公开(公告)日:2024-12-17
申请号:US18040944
申请日:2020-09-18
Applicant: Intel Corporation
Inventor: Shijie Liu , Tao Xu , Lei Zhu , Yufu Li
Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.
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公开(公告)号:US20240281315A1
公开(公告)日:2024-08-22
申请号:US18570493
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Shijie Liu , Tao Xu , Lei Zhu , Kevin Yufu LI
IPC: G06F11/07
CPC classification number: G06F11/076 , G06F11/0745 , G06F11/0793
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that perform runtime recovery of processor links. An example non-transitory computer readable medium comprises instructions that, when executed, causes a machine to at least determine an onset of an error based on health of a central processor unit (CPU) port, calculate a figure of merit (FOM) yield for each of a plurality of adaptation tasks performed on a lane of the CPU port using a first preset coefficient of a plurality of preset coefficients, select a preset coefficient based on the calculated FOM, and trigger a link recovery mechanism, using the selected preset coefficient to initiate a link recovery process on the CPU port.
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公开(公告)号:US20240241805A1
公开(公告)日:2024-07-18
申请号:US18560270
申请日:2021-09-25
Applicant: Intel Corporation
Inventor: Tao Xu , Shijie Liu , Kevin Yufu Li , Lei Zhu , Sarathy Jayakumar
IPC: G06F11/20
CPC classification number: G06F11/2094 , G06F2201/85
Abstract: A disclosed example includes setting a corrected error threshold value for a memory rank; recording, in a corrected error bank record memory structure, corrected errors for memory banks in the memory rank; maintaining, in the corrected error bank record memory structure, counts of the corrected errors for the memory banks; and notifying runtime error handling circuitry in response to at least one of the counts of the corrected errors satisfying a threshold value.
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公开(公告)号:US20230281080A1
公开(公告)日:2023-09-07
申请号:US17969321
申请日:2022-10-19
Applicant: Intel Corporation
Inventor: Hao Wu , Tao Xu , Changpeng Guo , Hehe Li , Fengyi Zhang , Yanxin Zhao , Wenlong Zheng
CPC classification number: G06F11/1415 , G06F13/4221 , G06F2213/0026
Abstract: An apparatus comprising a first processor comprising first circuitry to track correctable errors detected by a first communication device of a second processor; and second circuitry to communicate with the second processor to initiate, based on the tracked correctable errors, a link recovery procedure for the first communication device.
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公开(公告)号:US20250104797A1
公开(公告)日:2025-03-27
申请号:US18970293
申请日:2024-12-05
Applicant: Intel Corporation
Inventor: Zhiguo Wei , Du Lin , Tao Xu , Yufu Li , Zhenfu Chai
Abstract: Example systems, apparatus, articles of manufacture, and methods that perform memory preservation to improve system reliability are disclosed. Example apparatus disclosed herein increment an error count after detection of an error associated with a memory cell. Example apparatus also isolate a system memory address of the memory cell based on the error count.
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公开(公告)号:US12167014B2
公开(公告)日:2024-12-10
申请号:US17996997
申请日:2020-05-22
Applicant: INTEL CORPORATION
Inventor: Changliang Wang , Mohammad R. Haghighat , Wei Hu , Tao Xu , Tianmi Chen , Bin Yang , Jia Bao , Raul Diaz
IPC: H04N7/12 , H04N19/172 , H04N19/46 , H04N19/85
Abstract: Systems, apparatuses and methods may provide for source device technology that identifies a plurality of object regions in a video frame, automatically generates context information for the video frame on a per-object region basis and embeds the context information in a signal containing the video frame. Additionally, playback device technology may decode a signal containing a video frame and embedded context information, identifies a plurality of object regions in the video frame based on the embedded context information, and automatically selects one or more post-processing configurations for the video frame on a per-object region basis.
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公开(公告)号:US12073226B2
公开(公告)日:2024-08-27
申请号:US17794856
申请日:2020-02-24
Applicant: Intel Corporation
Inventor: Ping Wu , Yingwen Chen , Lei Zhu , Zhenglong Wu , Tao Xu
IPC: G06F9/00 , G06F9/4401 , G06F9/50 , G06F1/24
CPC classification number: G06F9/4403 , G06F9/4411 , G06F9/5016 , G06F1/24 , G06F9/4401
Abstract: Systems, apparatuses and methods may provide for technology that initializes an integrated memory of a processor during a boot sequence and conducts a runtime initialization of an external system memory associated with the processor. The technology may also bypass the runtime initialization of the external system memory during the boot sequence.
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公开(公告)号:US20230246888A1
公开(公告)日:2023-08-03
申请号:US18010779
申请日:2020-07-15
Applicant: Intel Corporation
Inventor: Yang Wu , Howard Heck , Jingbo Li , Tao Xu
IPC: H04L25/03
CPC classification number: H04L25/03878
Abstract: Embodiments of the present disclosure may relate to a controller coupled to a re-driver, where the controller has one or more sensor ports to couple with sensor devices, with circuitry coupled with the sensor ports and a re-driver port to receive operational data from the sensor ports, and based on the received operational data identify an indication of a re-driver equalizer setting to be transmitted to the re-driver device. Embodiments are used to increase the stability of the re-driver and maintain link margins a crossed varied operational conditions of the re-driver. Other embodiments may be described and/or claimed.
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