Invention Grant
- Patent Title: Channel hole and bitline architecture and method to improve page or block size and performance of 3D NAND
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Application No.: US16419825Application Date: 2019-05-22
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Publication No.: US11296107B2Publication Date: 2022-04-05
- Inventor: Jun Liu
- Applicant: Yangtze Memory Technologies Co., Ltd.
- Applicant Address: CN Hubei
- Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee: Yangtze Memory Technologies Co., Ltd.
- Current Assignee Address: CN Hubei
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/1157 ; H01L29/10 ; H01L29/423 ; H01L21/28 ; H01L23/522 ; H01L27/11565 ; H01L27/11573

Abstract:
Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate, the alternating layer stack including a plurality of conductor/dielectric layer pairs. The memory device further includes a first column of vertical memory strings extending through the alternating layer stack, and a first plurality of bitlines displaced along a first direction and extending along a second direction. The first column of vertical memory strings is disposed at a first angle relative to the second direction. Each of the first plurality of bitlines is connected to an individual vertical memory string in the first column.
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