Invention Grant
- Patent Title: Power enhanced stacked chip scale package solution with integrated die attach film
-
Application No.: US16641221Application Date: 2017-09-29
-
Publication No.: US11302671B2Publication Date: 2022-04-12
- Inventor: Zhijun Xu , Bin Liu , Yong She , Zhicheng Ding
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP.
- International Application: PCT/CN2017/104496 WO 20170929
- International Announcement: WO2019/061330 WO 20190404
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/18 ; H01L25/00

Abstract:
An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.
Public/Granted literature
- US20200227387A1 POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED DIE ATTACH FILM Public/Granted day:2020-07-16
Information query
IPC分类: