Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US16687713Application Date: 2019-11-19
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Publication No.: US11309296B2Publication Date: 2022-04-19
- Inventor: Nan-Chun Lin , Hung-Hsin Hsu , Shang-Yu Chang Chien , Wen-Hsiung Chang
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/48 ; H01L21/56 ; H01L21/768 ; H01L21/48 ; H01L23/498 ; H01L23/00 ; H01L23/538 ; H01L23/31 ; H01L25/04 ; H01L25/065

Abstract:
A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.
Public/Granted literature
- US20200091126A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2020-03-19
Information query
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