Invention Grant
- Patent Title: Verification of instructions from main processor to auxiliary processor
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Application No.: US16322983Application Date: 2017-08-02
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Publication No.: US11314518B2Publication Date: 2022-04-26
- Inventor: Marco Macchetti , Nicolas Fischer , Jerome Perrine
- Applicant: NAGRAVISION SA
- Applicant Address: CH Cheseaux-sur-Lausanne
- Assignee: NAGRAVISION SA
- Current Assignee: NAGRAVISION SA
- Current Assignee Address: CH Cheseaux-sur-Lausanne
- Agency: Hoyng Rokh Monegier BV
- Agent David P. Owen
- Priority: EP16182872 20160804
- International Application: PCT/EP2017/069578 WO 20170802
- International Announcement: WO2018/024797 WO 20180208
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F21/55 ; G06F21/72 ; G06F30/327 ; G06F11/28

Abstract:
A method of monitoring execution in an execution environment of an operation, for example a cryptographic operation, comprising a sequence of instructions, is disclosed. Instructions sent in the sequence from a main processor to one or more auxiliary processors, for example cryptographic processors, to execute the operation are monitored and the sequence of instructions is verified using verification information. The method comprises enabling output from the execution environment of a result of the operation in response to a successful verification of the sequence, or generating a verification failure signal in response to a failed verification of the sequence.
Public/Granted literature
- US20190187994A1 SEQUENCE VERIFICATION Public/Granted day:2019-06-20
Information query