Invention Grant
- Patent Title: Self-aligned top via scheme
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Application No.: US16540497Application Date: 2019-08-14
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Publication No.: US11322402B2Publication Date: 2022-05-03
- Inventor: Ruilong Xie , Chih-Chao Yang , Carl Radens , Juntao Li , Kangguo Cheng
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, PC
- Agent L. Jeffery Kelly
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522

Abstract:
A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.
Public/Granted literature
- US20210050259A1 SELF-ALIGNED TOP VIA SCHEME Public/Granted day:2021-02-18
Information query
IPC分类: